1. Field of the Invention
The present invention relates to a semiconductor device and a method for the manufacture thereof, and more specifically to a semiconductor device having an NPN bipolar transistor (hereinafter referred to as “NPN transistor”) and a PNP bipolar transistor (hereinafter referred to as “PNP transistor”) that perform high-frequency operation on a common silicon substrate and a method for the manufacture thereof.
2. Background Art
In recent years, the speed performance of bipolar transistors for high frequencies has rapidly been improved by forming epitaxial layers as the base layers with a heterojunction, such as silicon germanium (SiGe). In such ICs for high frequencies, if a PNP transistor having a speed performance equivalent to the speed performance of an NPN transistor is available, more versatile functions can be realized. FIG. 17 shows a high-power amplifier of a push-pull constitution (Yoshiaki Sano, “Fundamentals and Practice of Analog Integrated Circuit Design”, Realize, p. 141). This example has a circuit constitution having an NPN transistor and a PNP transistor in each of the difference input stage, intermediate stage, and output stage, and each transistor needs the same degree of speed performance. If a PNP current mirror can be moved quickly, the application to a multistage amplifier of direct current coupling, not by capacitance coupling, can be considered. Therefore, a semiconductor device having a PNP transistor having a speed performance equivalent to the speed performance of an NPN transistor is strongly demanded.
As an example of semiconductor devices, wherein a vertical NPN bipolar transistor and a vertical PNP bipolar transistor each having a junction between an emitter, base and collector formed in the depth direction of a substrate, i.e., in the vertical direction of the substrate, are formed on the same substrate, Japanese Patent Laid-Open No. 2-272758 discloses a semiconductor device shown in FIG. 18. This device consists of a silicon substrate 10; an N+−type buried emitter layer 12; a P+-type buried collector layer 14; deep trench isolating insulation layers 30, 32 and 34; shallow trench isolation insulating layers 44, 46, 48, 50, and 52; P-type base layer 54; a P+−type base leading layer 9272 an N-type collector layer 56; an N+−type collector leading layer 78; a P+−type emitter layer 98; a P+−type emitter leading layer 96; insulating films 80, 82, 92, and 112; a base electrode 104 of the NPN transistor; an emitter electrode 108 of the NPN transistor; a base electrode 106 of the PNP transistor; and a collector electrode 110 of the PNP transistor. In FIG. 18, the NPN transistor operates upwardly, and the PNP transistor operates
As another example of semiconductor devices, wherein a vertical NPN bipolar transistor and a lateral PNP bipolar transistor each having a junction between an emitter, base, and collector formed in the direction perpendicular to the depth direction of a substrate, i.e., in the horizontal direction of the substrate, are formed on the same substrate, Japanese Patent No. 2565113 discloses a semiconductor device shown in FIG. 19. This device consists of a silicon substrate 1; an N+-type buried collector layer 2; an N−-type epitaxial layer 3; an isolating oxide layer 4; an N+-type collector leading region 3′; an N-type collector region 11; P-type base regions 12, 44; an N+-emitter region 13; a P-type collector region 21; an N-type intrinsic base region 22; an N+-type hole stopper region 32; a P-type emitter region 23; P-type leading films 7 and 8; an N-type leading film 9; insulating films 5 and 6; a base electrode 14 of the NPN transistor; an emitter electrode 15 of the NPN transistor; a collector electrode 16 of the NPN transistor; a base electrode 24 of the PNP transistor; an emitter electrode 25 of the PNP transistor; and a collector electrode 26 of the PNP transistor. In FIG. 19, the NPN transistor operates downwardly, and the PNP transistor operates laterally.
For realizing high-speed operation, it is effective to shorten the time when the carrier passes through the base by narrowing the base width as much as possible. However, in the case of a vertical transistor as shown in FIG. 18, the base width of the NPN transistor is necessarily the same as the width of the collector of a low concentration of the PNP transistor. On the other hand, for obtaining a desired withstand voltage, the width of the collector of a low concentration cannot be narrowed than a predetermined value. Therefore, since the speed performance of a device is limited by the withstand voltage determined by the collector width, there is a problem of difficulty in forming a device that realizes high-speed performance while maintaining practical withstand voltage.
In a lateral transistor as shown in FIG. 19, since the base width depends on the resolution in the lithography process, and the formation of a narrow base width is difficult, there is a problem of speed performance inferior to the speed performance of a transistor of vertical operation. Furthermore, in a PNP transistor having the arrangement of the emitter and the collector as shown in FIG. 19, since the injection efficiency of the emitter cannot be raised, there is another problem of difficulty to obtain a high amplification ratio.
An example wherein a vertical NPN transistor and a vertical PNP transistor are formed on a single substrate (FIG. 20) is described in U.S. Pat. No. 5,930,635. In the structure shown in FIG. 20, however, if the base width is narrowed for high-speed operation, the base leading portions (portions indicated as p++SiGe and n++SiGe in FIG. 20) is also thinned, and there is a problem of the increase of the base resistance.